1. Field
The present technology relates to flash memory technology, and more particularly to charge trapping memory technology adaptable for high speed erase and program operations that is less susceptible to erase saturation despite high magnitude gate voltages.
2. Description of Related Art
Charge trapping memory is a class of non-volatile integrated circuit memory technology which stores data by employing dielectric charge trapping material to store charge. According to the early designs referred to as SONOS devices, the source, drain and channel are formed in a silicon channel material (S), the tunnel dielectric layer is formed of silicon oxide (O), the charge storage layer is formed of silicon nitride (N), the blocking dielectric layer is formed a silicon oxide (O), and the gate comprises polysilicon (S).
FIG. 1 shows a charge trapping memory cell which consists of a field effect transistor (FET) structure having a source 11 and drain 12 separated by a channel 10, and a gate 18 separated from the channel by a stack of dielectric material including a multi-layer tunnel dielectric structure 13-15, the charge storage layer 16, and a blocking dielectric layer 17.
The SONOS device is programmed by electron tunneling using one of a number of well-known biasing technologies, and erased by hole tunneling or electron de-trapping. In order to achieve practical operational speeds for the erase operation, the tunneling dielectric layer must be quite thin (less than 30 Å). However at that thickness, the endurance and charge retention characteristics of the memory cell are poor relative to traditional floating gate technology. Also, with relatively thick tunneling dielectric layers, the electric field required for the erase operation also cause electron injection from the gate through the blocking dielectric layer. Erase generally requires a high electric field magnitude of greater than about 15 MV/cm. This electron injection causes an erase saturation condition in which the charge level in the charge trapping device converges on an equilibrium level. See, U.S. Pat. No. 7,075,828, entitled “Operation Scheme with Charge Balancing Erase for Charge Trapping Non-Volatile Memory”, invented by Lue et al.
On one hand, technology has been investigated to improve the performance of the tunneling dielectric layer for erase at lower electric fields. In FIG. 1, the tunneling dielectric layer includes the 3 layer bandgap engineered structure 13-15 including layers of silicon oxide, silicon nitride, and silicon oxide.
FIG. 3 is a graph of flat band voltage versus erase time for the memory cell of FIG. 1. The BE-SONOS memory cell has a p polysilicon gate. Simulation of an erase operation with a −14 V gate voltage results in curve 310. Experimental data from an erase operation with a −14 V gate voltage results in plot points 311. Simulation of an erase operation with a −15 V gate voltage results in curve 320. Experimental data from an erase operation with a −15 V gate voltage results in plot points 321. Simulation of an erase operation with a −16 V gate voltage results in curve 330. Experimental data from an erase operation with a −16 V gate voltage results in plot points 331. Simulation of an erase operation with a −17 V gate voltage results in curve 340. Experimental data from an erase operation with a −17 V gate voltage results in plot points 341. Simulation of an erase operation with a −18 V gate voltage results in curve 350. Experimental data from an erase operation with a −18 V gate voltage results in plot points 351.
The curves and plot points for the lower magnitude gate voltages show an overly slow erase. The curves and plot points for the higher magnitude gate voltages are faster, but undergo erase saturation within 1 second or less. As more electrons are injected and stored in the first trapping layer (N2), the top oxide (O3) has a large electric field that induces a high gate injection.
On the other hand, technology has been investigated to improve the ability of the blocking dielectric layer to reduce electron injection from the gate for the high electric fields needed for erase. Prior art technologies have emphasized the advantages of high-K dielectrics like aluminum oxide. The higher dielectric constant can improve performance by enhancing the program and erase speed, improving the memory window in threshold voltage for the cells, and reducing the operating voltage during program and erase by reducing the effective oxide thickness EOT. However, it can be difficult to manufacture high-K materials like aluminum oxide with high quality. Therefore, the use of high-K materials for the blocking dielectric comes with the trade-off of lower reliability and lower data retention. For example, high-K materials easily generate shallow traps (or dipole relaxation) that causes a fast initial charge loss, leading to threshold voltage offsets in program verify values.
In FIG. 2, the blocking dielectric includes a high-K dielectric layer 17B and a silicon oxide layer 17A. FIG. 4 is a graph of flat band voltage versus erase time for a variation of the memory cell of FIG. 2 omitting silicon oxide layer 17A. In the curves and plot points, an erase operation is performed with a gate voltage of −18 V with N2 charge storage nitride layer 16 and high-K blocking dielectric layer 17B—having respective thicknesses 70 Å and 150 Å. The various curves and plot points are shown for different combinations of O1/N1/O2—oxide tunneling layer 13, nitride tunneling layer 14, oxide tunneling layer 15. An erase operation with O1/N1/O2 of 15 Å/20 Å/30 Å results in simulated curve 410 and experimental data plot points 411. An erase operation with O1/N1/O2 of 18 Å/20 Å/30 Å results in simulated curve 420 and experimental data plot points 421. An erase operation with O1/N1/O2 of 20 Å/20 Å/30 Å results in simulated curve 430 and experimental data plot points 431. Again, the curves and plot points for the lower magnitude gate voltages show an overly slow erase. Again, the curves and plot points for the higher magnitude gate voltages are faster, but undergo erase saturation within 1 second or less.
FIG. 5 is a graph of flat band voltage versus erase time for the memory cell of FIG. 2. In the curves and plot points, an erase operation is performed with a gate voltage of −15 V with O1/N1/O2/N2—oxide tunneling layer 13, nitride tunneling layer 14, oxide tunneling layer 15, charge storage nitride layer 16—having respective thicknesses 13 Å, 20 Å, 25 Å, and 50 Å. The various curves and plot points are shown for different combinations of O3 oxide blocking layer 17A, and high-K blocking dielectric layer 17B. An erase operation with O3/Al2O3 of 40 Å/60 Å results in simulated curve 510 and experimental data plot points 511 having respective thicknesses 70 Å and 150 Å. An erase operation with O3/Al2O3 of 50 Å/60 Å results in simulated curve 520 and experimental data plot points 521. Again, the curves and plot points for the lower magnitude gate voltages show an overly slow erase.
The high-K material such as Al2O3 or HfO2 thin films on top of O3 can help to reduce the E field of top dielectric, since higher-K results in smaller electric field in O3, which in turn reduces the erase saturation. However, the introduction of high-K material can result in significant reliability degradation such as worse retention, and vulnerability to some fast initial retention drift. For example, high-K materials have relaxation effects of delays in the dielectric constant, varying from the linear steady state dielectric constant.
An alternative to high-K material to overcome erase saturation is to introduce a curvature into the memory cell. For example, a nanowire cell has a central body; concentric rings with increasing diameters including a tunnel oxide ring, a silicon nitride ring, and a blocking oxide ring; and a surrounding gate. However, a sufficiently small curvature to enhance the electric field tends to cause program and read disturb effects.
BE-SONOS technology has been proven to provide excellent performance, overcoming many of the erase speed, endurance and charge retention issues of prior art SONOS type memory. However, the problem of the erase saturation continues to limit operational parameters of the device. Furthermore, as the device sizes shrink, it is expected that erase saturation problems will intensify.
Accordingly, is desirable to provide a new memory technology which is readily manufactured with high quality, and overcomes the erase saturation issues of prior art technologies.